1. Field of the Invention
The present invention relates to a semiconductor neural network and a method of driving the same, and more particularly, it relates to the structure of a semiconductor neural network which implements stable and high-speed operation with low power consumption and to a method of driving the same.
2. Description of the Background Art
In recent years, various electronic circuits have been implemented modeling themselves on human nerve cells (neurons). One of such neuron models is called a Hopfield model. This Hopfield model is now briefly described.
FIG. 1 schematically shows the structure of a unit which is modeled on a neuron. This unit i includes an input part A which receives signals from other units k, j and the like, a conversion part B which converts the received inputs along a predetermined rule and an output part C which outputs the results of conversion. The input part A has weights (synapses) W showing strengths of connection between the unit i and other input units. Thus, a weight Wik is added to a signal Sk from the unit k, which is transmitted to the conversion part B. Each weight W can take a positive value, a negative value or zero. The conversion part B outputs the sum net of the inputs S to which the weights W are added, through a predetermined function f. An output S.sub.i from the unit i at a time t is provided as follows: ##EQU1## A threshold function shown in FIG. 2A or a sigmoid function shown in FIG. 2B is generally employed as the function f.
The threshold function shown in FIG. 2A is a unit step function which outputs "1" when the sum net(i) of the inputs exceeds a threshold value .theta., while otherwise outputting "0".
The sigmoid function shown in FIG. 2B is a nonlinear, monotonously increasing function which is expressed as: EQU f=1/[1+exp(-net(i))]
This sigmoid function, which is in a range of zero to 1, approaches "0" as the sum net(i) of the inputs decreases, while approaching "1" as the sum net(i) increases. This sigmoid function outputs "0.5" when the sum net(i) is "0".
A threshold value .theta. may be added to the aforementioned sigmoid function, thereby to use a function which is expressed as: EQU f=1/[1+exp(-net(i)+.theta.)]
The aforementioned unit is modeled on a vital nerve cell which receives stimuli from other neurons to generate (fire) an output or to fire when the sum of the stimuli exceeds a given value. The Hopfield model provides an operating model of a network which is formed by a plurality of such modeled neurons.
When initial states are supplied to respective neuron units in the aforementioned equations (1), the states of the respective neuron units are thereafter entirely determined in principle by simultaneously applying the aforementioned two dynamic equations (1) to all the neuron units and solving the same. If the number of the units increases, however, it is almost impossible to examine and grasp the states of the respective units one by one for programming weight and bias values in order to provide optimum solutions to a target problem. Therefore, Hopfield introduces an energy function which is defined as: ##EQU2## as a quantity expressing the property of the overall system (neural network) in place of the states of the respective units. Symbol Ii represents a self-bias value which is specific to a unit i. Hopfield has indicated that, when a weight (synapse load) Wij is symmetrical as Wij=Wji, each unit changes its state to regularly minimize the aforementioned energy function to the local minimum, and proposed to apply this model to programming of the weight Wij. The model having the aforementioned energy function is called a Hopfield model. The aforementioned model is generally expressed as follows: EQU Ui(n)=.SIGMA.WijSj(n)+Ii EQU Si(n+1)=F[Ui(n)]
as a discrete time model. Symbol n represents a discrete time. Hopfield himself has indicated that this Hopfield model is realized particularly in high accuracy when the slope of the function f showing input/output characteristics is abrupt (a function approximate to a unit step function with which almost all outputs take values close to "0" or "1").
A neural network constructed in a VLSI (very large scale integrated circuit) in accordance with the Hopfield model, is disclosed in "Computer", a magazine issued by IEEE (Institute of Electrical and Electronics Engineers), March 1988, pp. 41-49, for example.
FIG. 3 schematically shows overall structure of a conventional neural network integrated circuit. Referring to FIG. 3, the conventional neural network integrated circuit includes a resistive matrix 100 which is formed by an array of resistive coupling elements having predetermined weights and an amplifier circuit 101 which amplifies potentials on data input lines included in the resistive matrix 100 and feeds back the amplified signals to input parts of the resistive coupling elements. The resistive matrix 100 includes data input lines and data output lines which are arrayed orthogonally to the data input lines, as hereinafter described in detail. Interconnection states of the data output lines to the data input lines through the resistive coupling elements are programmable.
A row decoder 102 and a bit decoder 103 are provided in order to program the states of the respective resistive coupling elements included in the resistive matrix 100, i.e., the interconnection states between the data input lines and the data output lines. The row decoder 102 selects a row of the resistive matrix 100, while the bit decoder 103 selects a column thereof.
The circuit further includes an input/output data register 104 which temporarily latches input/output data, a multiplexer 105 which connects the input/output data register 104 to the data input lines or the data output lines included in the resistive matrix 100 in response to a data write/read mode and an interface (I/O) 106 for connecting the input/output data register 104 to the exterior of the circuit, in order to input or output data. This neural network is integrated on a semiconductor chip 200. FIG. 4 illustrates exemplary structure of the resistive matrix 100 shown in FIG. 3.
Referring to FIG. 4, the resistive matrix 100 includes data input lines A1 to A4 and data output lines B1 and B1, B2 and B2, B3 and B3, and B4 and B4. Resistive coupling elements 1 are provided on crosspoints of the data input lines A1 to A4 and the data output lines B1 and B1 to B4 and B4. The resistive coupling elements 1 can enter open, excitatory and inhibitory states. The states of the resistive coupling elements 1 can be programmed from the exterior in accordance with an applied problem. While FIG. 4 shows no resistive coupling elements which are in the open states, the resistive coupling elements 1 are provided in all the crosspoints between the data input lines and the data output lines. The resistive coupling elements 1 transmit potential levels on the corresponding data output lines onto the corresponding data input lines in accordance with the programmed states respectively.
The input lines A1 to A4 are respectively provided with inverting amplifiers 2-1 to 2-8 which amplify the data on the corresponding data input lines and transmit the same onto the corresponding data output lines. Each pair of series-connected inverters function as one amplifier unit. The inverter 2-1 inverts the potential on the data input line A1 and transmits the same onto the data output line B1. The inverter 2-2 transmits the data on the data input line A1 onto the data output line B1. The inverter 2-3 transmits inverted data from the data input line A2 onto the data output line B2, and the inverter 2-4 transmits the data on the data input line A2 onto the data output line B2. The inverters 2-5 and 2-6 invert and transmit the potential on the data input line A3 onto the data output lines B3 and B3 respectively. The inverters 2-7 and 2-8 invert and transmit the potential on the data input line A4 onto the data output lines B4 and B4 respectively.
Each of the coupling elements 1 connects the output of an amplifier to the input of another amplifier. FIG. 5 shows exemplary structure of each coupling element.
Referring to FIG. 5, the resistive coupling element 1 includes resistor elements R+ and R-, switching elements S1, S2, S3 and S4 and random access memory cells 150 and 151. An end of the resistor element R+ is connected to a source potential V.sub.DD. The resistor element R- is connected to another source potential V.sub.SS. The switching element S1 is on-off controlled by the output of an amplifier (inverter) 2b. The switching element S2 is on or off controlled by the random access memory cell 150. The ON/OFF state of the switching element S3 is set by the random access memory cell 151. The switching element S4 is on or off controlled by the output of an inverter 2a. Output states of the random access memory cells 150 and 151 can be previously programmed from the exterior, and hence ON/OFF states of the switching elements S2 and S3 can be also previously programmed.
In the structure shown in FIG. 5, the output of the amplifier circuit Ci (circuit formed by the inverters 2a and 2b) directly supplies no current to the corresponding input line. Thus, output load capacitance of the amplifier Ci is reduced. The resistor elements R+ and R- are current limit resistors.
The coupling element 1 can enter one of three states according to program states of the random access memory cells 150 and 151. The three states include an excitatory connection state in which the switching element S2 is in an ON state (active state), an inhibitory connection state in which the switching element S3 is in an active state (ON state) and an open connection state in which both of the switching elements S2 and S3 are in inactive states (OFF states). When potential levels of the output lines Bi and Bi of the amplifier circuit Ci match with the programmed connection state of a given resistive coupling element 1, a current flows to the corresponding input line Ai from either the source potential V.sub.DD or the other source potential (ground potential V.sub.SS. When the resistive coupling element 1 is programmed in the open connection state, no current is transmitted to the input line Ai regardless of the output state of the amplifier circuit Ci.
When the aforementioned circuit model is associated with a neuron model, the amplifier circuit Ci corresponds to a neuron body (conversion part B in FIG. 1). The interconnections A1 to A4, B1 to B4 and B1 to B4 correspond to the data input and output line structure parts (dendrites and axons) shown in FIG. 1. The resistive coupling elements 1 correspond to the synapse load parts provided between the neurons for adding weights. The operation is now briefly described.
The model shown in FIG. 4 is often called a connectionist model. In this model, each neuron unit (amplifier circuit) merely thresholds an input signal, i.e., outputs a signal which corresponds to the value of the input signal with respect to a predetermined threshold value. Each resistive coupling element 1 connects the output of a given amplifier circuit to the inputs of other amplifier circuits. Thus, the state of each amplifier circuit Ci is determined by the states of all the remaining amplifier circuits Cj. When a given amplifier circuit Ci detects the current of a corresponding input line Ai (i=1 to 4), the output of the amplifier circuit Cj is provided as follows: ##EQU3## where Vin(i) and Vout(i) represent input and output voltages of the amplifier circuit Ci which is connected to the data input line Ai, Ii represents a current flowing in one resistive coupling element 1 and Wij represents conductance of the resistive coupling element connecting the amplifier circuit Ci, which is connected to the data input line Ai, with the amplifier circuit Cj which is connected to the data input line Aj. The output voltage Vout(i) of each amplifier circuit Ci is provided by the transfer characteristic of the amplifier circuit Ci itself. An amplifier circuit C' (inverters 2a and 2b) supplies no current to any data input line, but merely controls on-off operation of the switching elements S1 and S4. Thus, the output load of the amplifier circuit C' is reduced to the data output line capacitance. The voltage of the input line Ai of a given amplifier circuit Ci is provided by the sum of currents flowing into the input line Ai. This voltage is adjusted to a value where the total current is zero. That is, the total energy of this electronic network is minimized at this time.
Each amplifier circuit Ci is formed by a CMOS inverter, for example, the input impedance of which is high and has the aforementioned nonlinear, monotonously increasing threshold function. In this case, the following relation holds from the aforementioned condition that the total current is zero: ##EQU4## where symbol Iij represents a current flowing through the resistor of the resistive coupling element which is controlled by the output of the amplifier circuit Ci connected to the input line Ai. Symbol .DELTA.Vij represents potential difference in the resistive coupling element, which potential difference is provided as follows: ##EQU5## Symbol Rij represents resistance of the resistive coupling element, which resistance is provided as R+ or R-. Thus, the voltage Vin(i) is the total sum of all outputs of the amplifier circuits which are connected to the data input lines Ai.
The amplifier circuit C' functions as a high-gain threshold element. The threshold value of the amplifier circuit C' is generally set at about 1/2 of the source potentials V.sub.SS and V.sub.DD.
The above is analog calculation, which is performed within the resistive matrix 100 in a parallel manner. However, both the input and output data are digital data. Actual arithmetic operation is now briefly described with reference to FIG. 4.
The neural network is initialized when input data are supplied onto the respective input lines A1 to A4 through the register 10, so that the input lines A1 to A4 are charged at values corresponding to the input data. Output potentials of the amplifier circuits C1' to C4' are first changed in response to the charging potentials supplied to the input lines A1 to A4. Such potential changes on the data output lines are fed back to the data input lines A1 to A4 through corresponding resistive coupling elements. The potential levels fed back to the respective data input lines A1 to A4 are determined by program states of the respective resistive coupling elements 1. When a given resistive coupling element 1 is programmed in excitatory connection, a current flows from the source potential V.sub.DD to an input line Ai. When the resistive coupling element 1 is programmed in an inhibitory connection state, on the other hand, a current flows from the data input line Ai into the ground line V.sub.SS. Such operations progress in a parallel manner in the matrix except for resistive coupling elements which are in open connection states, so that currents flowing into a given data input line Ai are added up in an analog manner thereby to change the potential at the data input line Ai. When such changed potential of the data input line Ai exceeds the threshold voltage of a corresponding inverting amplifier circuit Ci', the output potential of this amplifier circuit Ci' is changed. Such a state is repeated and the outputs of the amplifier circuits Ci' are so changed as to satisfy the aforementioned condition that the total current is zero. The state of the network is finally stabilized to satisfy the aforementioned equation (2) for the stabilized state. After the state of the neural network is stabilized, the output voltages of the respective amplifier circuits Ci' are stored in a register and thereafter read out. A decision of the stabilized state of the neural network is set by a predetermined time after data input, or made by directly comparing data stored in the register with each other wherein a decision is made that the neural network is stabilized when difference between the compared output data is below a predetermined value, to obtain the data output.
As described above, data minimizing the energy of the neural network are outputted as the output data. The resistive matrix 100 stores certain patterns and certain data in accordance with the program states of the resistive coupling elements 1. Therefore, the neural network, which can decide match/mismatch of the stored patterns or data and input data, also functions as an associative memory or a pattern discriminator.
Structure known as a single-layer perceptron circuit is obtained by removing feedback paths from the data output lines Bi and Bi to the data input lines Aj from the resistive matrix 100 shown in FIG. 4. This perceptron circuit, for which a learning algorithm is readily made, can be so multi-layered as to construct a flexible system.
In the aforementioned neural network, the data output lines are formed by the complementary line pairs Bi and Bi thereby to implement excitatory connection and inhibitory connection, for increasing the speed of convergence of the network to a stable energy state.
In this conventional neural network, the amplifier circuit Ci' for transmitting a potential level corresponding to that on the data input line Ai onto the data output lines Bi and Bi is prepared by an inverter (inverting amplifier). Therefore, the data conversion function f of the neuron unit is defined by data input/output characteristics of the inverter. Further, inversion/non-inversion of the potential level in transmission of the potential of the data input line Ai onto the data output line Bi is determined by the input logic threshold value of the inverter. This input logic threshold value is generally set at 1/2 of the sum of the source potential V.sub.DD and the ground potential V.sub.SS. While the sigmoid-like nonlinear, monotonously increasing function may be employed as hereinabove described, the total input providing the output data "0.5" must be decided to be zero in this case. Further, a conversion function which is obtained by adding a threshold value to the sigmoid-like, monotonously increasing function may also be employed as hereinabove described.
In general, the input logic threshold value of an inverting amplifier having CMOS (metal-insulating film-semiconductor) structure is determined with parameters of the size of a transistor, i.e., impedance (ON resistance), the threshold voltage of the transistor and the like.
Alternatively, the input logic threshold voltage may be replaced by a reference voltage which is generated within the chip, so that inversion/non-inversion of data in data transmission is determined by large/small comparison of the reference voltage and the voltage level on the data input line Ai.
In each structure, threshold voltages and sensitivity of the inverting amplifier circuits for converting data serve as important factors determining the performance of the neural network. Therefore, it is preferable to minimize deviation of the threshold voltages in the inverting amplifier circuits between chips or within a chip.
However, as a semiconductor circuit implementing a neural network is fined down and/or increased in scale, variations in fabrication parameters (processing temperature, misalignment of masks in patterning, impurity concentration etc.) change transistor characteristics, and if the amplifier circuits are implemented by series-connected inverting amplifiers as in the aforementioned prior art, it is difficult to set the threshold voltages and sensitivity of the amplifier circuits at constant values without causing deviation thereof between chips and within a chip.
Further, the comparison reference voltage providing the threshold values cannot be stably generated. In general, such comparison reference voltage is generated by providing voltage drop to the source voltage V.sub.DD through a voltage-drop circuit which is formed by diode-connected MOS (metal-insulating film-semiconductor) transistors or the like. Therefore, a stable reference voltage of a desired value cannot be generated due to the aforementioned variations in transistor characteristics (threshold voltage, ON resistance etc.) and in the source voltage V.sub.DD, and hence the data conversion characteristics of the amplifier circuits cannot be obtained as designed.
Such variations in the threshold voltages of the amplifier circuits and in the reference voltage change amplifying characteristics of the amplifier circuits, to lead to such malfunctions that the data processing speed, correspondence between input data and output data etc. are varied with semiconductor neural networks to damage reliability of the semiconductor neural networks.
On the other hand, it is known that a Boltzmann model (Boltzmann machine) is obtained by regarding the energy function in the Hopfield model as a probability variable and extending the algorithm of Hopfield to a probability system. FIG. 6 shows exemplary structure of an essential part of a semiconductor neural network in accordance with the Boltzmann model. This structure is disclosed in, for example, "Neuromorphic VLSI Learning System" in "Advanced Research in VLSI 1987" issued by MIT Press, pp. 313-327.
Referring to FIG. 6, neuron units are respectively formed by differential amplifiers Zl to Zj each having two complementary outputs S and S. When a neuron is in an "ON" state, its output S is "1" (5 V), and when the neuron is "OFF", the output S is "0" (0 V). The output of each neuron unit (differential amplifier) is fed back to respective differential inputs IN and IN through resistive elements R. The resistive elements R, which have conductances changeable, define weights Wij. Self-bias parts 400 are provided to apply self-bias values -.theta. to respective input lines IN and IN. Data of "1" and "0" are steadily applied to the self-bias parts 400 through a differential amplifier Z.sub.T. The diagonally arranged differential amplifiers correspond to nerve cells, and perform thresholding processing. The input lines IN and IN correspond to dendrites receiving signals from other cells. The data input lines IN and IN transmit excitatory and inhibitory signals respectively. The output lines S and S correspond to axons which transmit signals from given neurons to next neurons. The resistive elements R correspond to synapses, whose resistance values indicate connection strengths between the neurons.
The resistive elements R, which are arranged at nodes between the data input lines INi and INi and the data output lines Sj and Sj, i.e., the positions of I-th row and J-th column (i, j), can connect the output of a neuron (differential amplifier) Zj to the input of a neuron (differential amplifier) Zi, to provide a positive weight Wij. In the case of the positive weight Wij, a data output line Sj is connected to a data input line INi while a data output line Sj is connected to a data input line INi. In the case of a negative weight coefficient, the data output line Sj is connected to the data input line INi, while the data output line Sj is connected to the data input line INi.
This neural network is initialized by setting the resistance values of the resistive elements R. A subject in the Boltzmann model is to find weights Wkl, with which the neural network itself can implement probability distribution of input/output data "as correct as possible", without supplying the distribution from the exterior. To this end, a weight processor (not shown) is provided for each weight Wkl. This weight processor has a function of latching weight data while shifting the latch data, as well as a function of incrementing or decrementing the latch data in accordance with a predetermined relational expression after each operation loop (+phase, -phase etc.).
The algorithm of the Boltzmann model includes operation 1 (plus phase), operation 2 (minus phase), operation 3 (change of Wkl) and operation 0 (learning of output layer).
The operation 1 includes an annealing process, a data collection process and a process of obtaining P.sup.+. The annealing process is carried out by applying an externally generated analog noise signal, whose amplitude is decreased with progress of the operation, to the differential inputs of each differential amplifier. This means that the annealing process is started at a high temperature and thereafter the temperature is sequentially changed to low levels, whereby the neural network system is stabilized to the minimum global energy value of a thermal equilibrium state at a low temperature. This state is caused in each differential amplifier Z, and the differential amplifier Z evaluates the state of itself to set its state "ON" or "OFF". The data collection process is adapted to obtain the number of times when both of respective states of two interconnected neurons (differential amplifiers) are "1". The process of obtaining P.sup.+ is adapted to obtain an average value of data obtained in the data collection process.
The operation 2 (minus phase) is adapted to carry out the aforementioned three processes of the operation 1 while fixing only states of neurons (differential amplifiers) corresponding to input data at "1". A value obtained in a process of obtaining an average value in the operation 2 is assumed to be P.sup.-.
The operation 3 is a process of changing the weights Wkl by the average values P.sup.+ and P.sup.- obtained through the operation 1 and the operation 2.
After the aforementioned operation 1 or operation 2, the respective weights Wkl are adjusted by parallel operation, and the weight processors provided in correspondence to the respective weights evaluate the states thereof to increment or decrement the weights. Since the data input/output lines are arrayed in pairs as hereinabove described, the weights adjust their own weights through the aforementioned parallel algorithm by themselves.
FIG. 7 shows an example of specific structure of a resistive element providing a weight WKl. Referring to FIG. 7, a weight part includes four transistor groups TR1, TR2, TR3 and TR4 for providing positive connection and negative connection. Each of the transistor groups TR1 to TR4, which are identical in structure to each other, includes n MOS transistors T0 to Tn-1 and a pass transistor TG.
Conductance ratios of the MOS transistors T0 to Tn-1 (width/length ratios of the transistors) are set as 1:2: . . . :2.sup.n-1. The pass transistor TG receives either a sign bit TSGN or TSGN for indicating the sign (positive or negative) of connection, to connect a data input line with a corresponding data output line. Since the transistor groups provided on a diagonal line simultaneously connect data input and output lines, the positive sign bit TSGN is applied to transfer gates TG1 and TG4, while the inverted sign bit TSGN is applied to transfer gates TG2 and TG3. The weight coefficient Wij can be set by making an ON state through appropriate combination of the transistors T0 to Tn-1 in each transistor group.
FIG. 8 shows an example of specific structure of a differential amplifier forming a neuron.
Referring to FIG. 8, the differential amplifier includes four N-channel MOS transistors NT1, NT2, NT3 and NT4 and two P-channel MOS transistors PT1 and PT2. The MOS transistors NT1 and NT2 form a first differential inputs, and the MOS transistors NT3 and NT4 form a second differential inputs. The first differential inputs formed by the MOS transistors NT1 and NT2 receives noise from a noise source NS through a differential amplifier AZ. The first differential inputs formed by the MOS transistors NT1 and NT2 to generate an annealing temperature in the form of noise. The second differential inputs formed by the MOS transistors NT3 and NT4 differentially amplifies data on data input lines IN and IN. The second differential inputs calculate an energy gap between an "OFF" state and an "ON" state of a neuron unit (differential amplifier) k. Through employment of the noise source NS, it is intended that the state of the neural network goes out of a quasi-optimum solution which is called the local minimum, to converge to the optimum solution.
A differential output part formed by the MOS transistors PT1 and PT2 derives complementarily symmetrical signals indicating any states between "ON" and "OFF" states. In this case, potential levels transmitted to data output lines S and S are set at a source voltage level or a ground potential level. Thus, a pass transistor TG included in a weight creating part is reliably on or off controlled. A MOS transistor NT5 receiving a predetermined bias potential Vbias at its gate is provided in order to bring the differential amplifier into a constant operating state.
Two types of conductances are connected to the positive input (MOS transistor NT4 in FIG. 8) of the differential amplifier. One is a conductance for pulling up to a voltage Von (voltage transmitted through a positive weight), and the other one is a conductance for pulling down to a voltage Voff (voltage transmitted through a negative weight). The pullup conductance at the positive input is provided by the absolute value of the sum of positive weights from neurons (differential amplifiers) which are in "ON" states and negative weights from neurons (differential amplifiers) which are in "OFF" states. The pulldown conductance is provided by the sum of negative weights from neurons (differential amplifiers) which are in "ON" states and positive weights from neurons which are in "OFF" states. This relation is reversed for the negative input (transistor NT3 in FIG. 8) of the neuron (differential amplifier). The differential amplifier forming this neuron performs the following comparison, assuming that the neurons which are in the "ON" states are expressed as .delta.j=+1 and the neurons which are in the "OFF" states are expressed as .delta.j=-1: ##EQU6## where .theta.i represents self-bias values provided in correspondence to the respective neurons shown in FIG. 6. Transfer characteristics of the respective data inputs and outputs are defined in accordance with such states. This comparison is made by comparing the positive input of the differential amplifier with a threshold value 1/2 (Von+Voff). Such comparison requires completely matching transistors with each other. However, even if integration density is so enhanced that transistor matching is made incomplete to cause deviation in operating points, symmetrical output data can be derived therefrom and data can be correctly compared with great noise immunity by employing the aforementioned differential amplifier.
In this structure of the differential amplifier, however, the constant bias voltage Vbias is applied to the gate electrode of the MOS transistor NT5, and therefore, the neuron is formed by a static amplifier. In this case, the differential amplifier is regularly in an operating state from supply of power onward, and the amplifier is not inactivated. Thus, whereby power is unnecessarily used up in this differential amplifier. Further, such a static differential amplifier has rather insufficient sensitivity, and cannot reliably detect small potential difference on the data input lines IN and IN and amplify the same to a desired voltage level to output the same.
In this conventional structure, the neurons are formed by static differential amplifiers while no resetting (initialization) of data input and output lines is performed, and hence much time is required to charge or discharge the data input lines in correspondence to supplied input data. Thus, it takes much time to initialize the neural network. Further, since the data output lines are not reset, it takes much time to establish potentials of the data output lines. In the neural network employing such static differential amplifiers as neurons, therefore, much time is required to bring the network in a stable operating state upon supply of the input data, and hence the processing speed is reduced.
Further, when neuron units are formed by the aforementioned static differential amplifiers, it is difficult to synchronize the operation of this semiconductor neural network with that of an external data processor since all the neuron units are asynchronously operated. Thus, it is difficult to form one synchronous system incorporating conventional neural net.